Low power chip design and test technologies
W: Hardware – Software – Cybersecurity – Blockchain – Internet of things (IoT)
Informations
- Stand number
- D04
- Exhibition class
- W: Hardware – Software – Cybersecurity – Blockchain – Internet of things (IoT)
- Technical description
- Automatic phase-error correction technique was presented to improve energy efficiency of low-power chips by speeding up the clock startup. The chips were tested with an adaptive testing algorithm to guarantee the chip field.
- Simplified description
- A technique was introduced to make low-power chips more energy-efficient by quickly correcting phase errors when they start up. These chips were tested using a smart algorithm to ensure they perform well in real-world conditions.
Inventors
Nanjing University of Posts and Telecommunications
inventor 3701634007_4274
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