Informations

Stand number

B93

Exhibition class

W: Hardware – Software – Cybersecurity – Blockchain – Internet of things (IoT)

Technical description

S-RISC-V is a secure architecture with a lightweight RISC-V processor and security coprocessor, accelerating post-quantum cryptography by hundreds of times while using minimal FPGA resources to enhance IoT security against quantum threats.

Simplified description

S-RISC-V is a secure and efficient computing system designed for safe Internet of Things (IoT) applications. It uses a lightweight RISC-V processor paired with a security coprocessor to handle complex cryptographic tasks like elliptic curve and post-quantum cryptography. The technology has been successfully tested using FPGA to ensure its security.